XILINX_PCI_EXP_EP Project Status (03/03/2014 - 15:49:47)
Project File: | PCIe_Bus_master_xil_vhdl.xise | Parser Errors: | No Errors
Module Name: | ram_wrap | Implementation State: | Placed and Routed
Target Device: | xc5vlx110t-1ff1136 |

- Errors:

No Errors
Product Version: | ISE 14.7 |

- Warnings:

4 Warnings (4 new)
Design Goal: | Balanced |

- Routing Results:

All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

All Constraints Met
Environment: | System Settings |

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice LUTs | 167 | 69,120 | 1% |
Number used as logic | 167 | 69,120 | 1% |
Number using O6 output only | 164 |  |  |
Number using O5 and O6 | 3 |  |  |
Number of occupied Slices | 58 | 17,280 | 1% |
Number of LUT Flip Flop pairs used | 167 |  |  |
Number with an unused Flip Flop | 167 | 167 | 100% |
Number with an unused LUT | 0 | 167 | 0% |
Number of fully used LUT-FF pairs | 0 | 167 | 0% |
Number of slice register sites lost to control set restrictions | 0 | 69,120 | 0% |
Number of bonded IOBs | 181 | 640 | 28% |
Number of BlockRAM/FIFO | 2 | 148 | 1% |
Number using BlockRAM only | 2 |  |  |
Number of 36k BlockRAM used | 2 |  |  |
Total Memory used (KB) | 72 | 5,328 | 1% |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Number used as BUFGs | 1 |  |  |
Average Fanout of Non-Clock Nets | 2.65 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | pon 3. mar 15:48:33 2014 | 0 | 4 Warnings (4 new) | 1 Info (1 new)
Translation Report | Current | pon 3. mar 15:48:40 2014 | 0 | 0 | 0
Map Report | Current | pon 3. mar 15:49:07 2014 | 0 | 0 | 8 Infos (8 new)
Place and Route Report | Current | pon 3. mar 15:49:33 2014 | 0 | 0 | 3 Infos (3 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | pon 3. mar 15:49:45 2014 | 0 | 0 | 4 Infos (4 new)
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | pon 3. mar 15:47:32 2014

Date Generated: 03/03/2014 - 15:49:47