user_wrapper_for_pcie Project Status (03/07/2014 - 16:08:36)
Project File: | PCIe_Bus_master_xil_vhdl.xise | Parser Errors: | No Errors
Module Name: | user_wrapper_for_pcie | Implementation State: | Programming File Not Generated
Target Device: | xc5vlx110t-1ff1136 |

- Errors:

Product Version: | ISE 14.7 |

- Warnings:

Design Goal: | Balanced |

- Routing Results:

Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

Environment: | System Settings |

- Final Timing Score:

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 885 | 69,120 | 1% |
Number used as Flip Flops | 875 |  |  |
Number used as Latches | 10 |  |  |
Number of Slice LUTs | 1,626 | 69,120 | 2% |
Number used as logic | 1,625 | 69,120 | 2% |
Number using O6 output only | 1,351 |  |  |
Number using O5 output only | 4 |  |  |
Number using O5 and O6 | 270 |  |  |
Number used as exclusive route-thru | 1 |  |  |
Number of route-thrus | 5 |  |  |
Number using O6 output only | 5 |  |  |
Number of occupied Slices | 543 | 17,280 | 3% |
Number of LUT Flip Flop pairs used | 1,639 |  |  |
Number with an unused Flip Flop | 754 | 1,639 | 46% |
Number with an unused LUT | 13 | 1,639 | 1% |
Number of fully used LUT-FF pairs | 872 | 1,639 | 53% |
Number of unique control sets | 23 |  |  |
Number of slice register sites lost to control set restrictions | 35 | 69,120 | 1% |
Number of bonded IOBs | 172 | 640 | 26% |
Number of BlockRAM/FIFO | 2 | 148 | 1% |
Number using BlockRAM only | 2 |  |  |
Number of 36k BlockRAM used | 2 |  |  |
Total Memory used (KB) | 72 | 5,328 | 1% |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Number used as BUFGs | 1 |  |  |
Average Fanout of Non-Clock Nets | 5.45 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | pet 7. mar 15:15:50 2014 |  |  |
Translation Report | Current | pet 7. mar 15:27:00 2014 |  |  |
Map Report | Current | pet 7. mar 15:27:54 2014 |  |  |
Place and Route Report | Current | pet 7. mar 15:28:27 2014 |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | pet 7. mar 15:28:41 2014 |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | pet 7. mar 15:29:53 2014
WebTalk Report | Current | pet 7. mar 16:09:27 2014
WebTalk Log File | Current | pet 7. mar 16:09:33 2014

Date Generated: 03/07/2014 - 16:09:34