XILINX_PCI_EXP_EP Project Status (03/03/2014 - 16:00:47)
Project File: | PCIe_Bus_master_xil_vhdl.xise | Parser Errors: | No Errors
Module Name: | ram_wrap | Implementation State: | Placed and Routed
Target Device: | xc5vlx110t-1ff1136 |

- Errors:

No Errors
Product Version: | ISE 14.7 |

- Warnings:

2 Warnings (2 new)
Design Goal: | Balanced |

- Routing Results:

All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

All Constraints Met
Environment: | System Settings |

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 1,024 | 69,120 | 1% |
Number used as Flip Flops | 1,024 |  |  |
Number of Slice LUTs | 815 | 69,120 | 1% |
Number used as logic | 815 | 69,120 | 1% |
Number using O6 output only | 741 |  |  |
Number using O5 and O6 | 74 |  |  |
Number of occupied Slices | 651 | 17,280 | 3% |
Number of LUT Flip Flop pairs used | 1,829 |  |  |
Number with an unused Flip Flop | 805 | 1,829 | 44% |
Number with an unused LUT | 1,014 | 1,829 | 55% |
Number of fully used LUT-FF pairs | 10 | 1,829 | 1% |
Number of unique control sets | 16 |  |  |
Number of slice register sites lost to control set restrictions | 0 | 69,120 | 0% |
Number of bonded IOBs | 185 | 640 | 28% |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Number used as BUFGs | 1 |  |  |
Average Fanout of Non-Clock Nets | 3.96 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | pon 3. mar 15:59:18 2014 | 0 | 2 Warnings (2 new) | 1 Info (1 new)
Translation Report | Current | pon 3. mar 15:59:26 2014 | 0 | 0 | 0
Map Report | Current | pon 3. mar 15:59:59 2014 | 0 | 0 | 6 Infos (0 new)
Place and Route Report | Current | pon 3. mar 16:00:32 2014 | 0 | 0 | 3 Infos (1 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | pon 3. mar 16:00:45 2014 | 0 | 0 | 4 Infos (0 new)
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | pon 3. mar 15:47:32 2014

Date Generated: 03/03/2014 - 16:00:47