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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:50:28 02/25/2014 
-- Design Name: 
-- Module Name:    reg_bram - bram 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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--
-- Dual-Port RAM with Synchronous Read (Read Through)

--		16 x 64bitov
--
--
--
-- Read-First Mode
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

entity rams_11 is
   
   -- port definitions
   port( 
	     clk         : in std_logic;
		  
		  --primary (kompresor core)
        addr1       : in std_logic_vector(3 downto 0);
        out1A       : out unsigned(63 downto 0);
		  write_en1   : in std_logic;
        write_data1 : in unsigned(63 downto 0);

		  --dual (pcie)
		  addr2       : in std_logic_vector(3 downto 0);
        out2A       : out unsigned(63 downto 0);
        write_en2   : in std_logic;
        write_data2 : in unsigned(63 downto 0)
        );
    end entity rams_11;
 
architecture syn of rams_11 is
	type ram_type is array (15 downto 0) of unsigned (63 downto 0);
	signal RAM : ram_type;
	signal read_a : std_logic_vector(3 downto 0);
	signal read_b : std_logic_vector(3 downto 0);
begin

process (clk)
begin
	if (rising_edge(clk)) then
		if (write_en1 = '1') then
			RAM(conv_integer(addr1)) <= write_data1;
		elsif (write_en2 = '1') then
			RAM(conv_integer(addr2)) <= write_data2;
		end if;
		read_a <= addr1;
		read_b <= addr2;
	end if;
end process;

out1A <= RAM(conv_integer(read_a));
out2A <= RAM(conv_integer(read_b));

end syn;
