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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:02:12 02/25/2014 
-- Design Name: 
-- Module Name:    ram_wrap - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ram_wrap is
   port( 
	     clk         : in std_logic;
		  
		  --primary (pcie)
        addr1       : in std_logic_vector(3 downto 0);
        out1A       : out std_logic_vector(63 downto 0);
		write_en1   : in std_logic;
        write_data1 : in std_logic_vector(63 downto 0);

		  --dual (kompresor core)
		addr2       : in std_logic_vector(3 downto 0);
        out2A       : out std_logic_vector(63 downto 0);
        write_en2   : in std_logic;
        write_data2 : in std_logic_vector(63 downto 0)
        );
end ram_wrap;

-- BRAM, 16 x 64 bitov
architecture Behavioral of ram_wrap is
component rams_11 
   port( 
	     clk         : in std_logic;
		  
		  --primary (kompresor core)
        addr1       : in std_logic_vector(3 downto 0);
        out1A       : out std_logic_vector(63 downto 0);
		write_en1   : in std_logic;
        write_data1 : in std_logic_vector(63 downto 0);

		  --dual (pcie)
		addr2       : in std_logic_vector(3 downto 0);
        out2A       : out std_logic_vector(63 downto 0);
        write_en2   : in std_logic;
        write_data2 : in std_logic_vector(63 downto 0)
        );
end component;

signal dout2	: std_logic_vector (63 downto 0);	--prebrano iz rama(za kompresor), 
signal din2		: std_logic_vector (63 downto 0); 	--v ta signal zlepimo za zapis iz kompresorja
signal addr1	: std_logic_vector(3 downto 0);
signal addr2  	: std_logic_vector(5 downto 0);

begin
ram: rams_11 port map (
	clk=>clk,
	
	addr1=>addr1,
	out1A=>out1,
	write_en1=>write_en1,
	write_data1=>din1,
	
	addr2=>addr2(5 downto 2),
	out2A=>dout2,
	write_en2=>write_en2,
	write_data2=>write_data2

);

busy1<=write_en1;
busy2<=write_en2;
addr1<=addr_wr1 when write_en1='1' else addr_rd1;
addr2<=addr_wr2 when write_en2='1' else addr_rd2;

--	16-64 bit adaptation - dual read
out2 <= 	dout2(15 downto 0) when addr2(1 downto 0)="00" else
			dout2(31 downto 16) when addr2(1 downto 0)="01" else
			dout2(47 downto 32) when addr2(1 downto 0)="10" else
			dout2(63 downto 48);
--	16-64 bit adaptation - dual write
din2 <= 	(dout2(63 downto 16) & write_data2) 							when addr2(1 downto 0)="00" else
			(dout2(63 downto 32) & write_data2 & dout2(15 downto 0)) when addr2(1 downto 0)="01" else
			(dout2(63 downto 48) & write_data2 & dout2(31 downto 0)) when addr2(1 downto 0)="10" else
			(write_data2 & dout2(47 downto 0));

-- process (clk)
-- begin
-- if (rising_edge(clk)) then
	-- case ( addr1(1 downto 0) ) is
		-- when "00" =>
			-- out1<=dout1(15 downto 0);
			-- din1<=dout1(63 downto 16) & write_data1;
		-- when "01" =>
			-- out1<=dout1(31 downto 16);
			-- din1<=dout1(63 downto 32) & write_data1 & dout1(15 downto 0);
		-- when "10" =>
			-- out1<=dout1(47 downto 32);
			-- din1<=dout1(63 downto 48) & write_data1 & dout1(31 downto 0);
		-- when others =>
			-- out1<=dout1(63 downto 48);
			-- din1<=write_data1 & dout1(47 downto 0);
	-- end case;
-- end if;
-- end process;


end Behavioral;

