----------------------------------------------------------------------------------
-- Company: IJS 
-- Engineer: Gasper Kojek
-- 
-- Create Date:    14:41:41 02/25/2014 
-- Last edit:      12:35    03/04/2014
-- Design Name:    Register block
-- Module Name:    reg_PIO - Behavioral 
-- Project Name: 
-- Target Devices:  Xilinx Virtex 5
-- Tool versions:   Xilinx ISE 14.7
-- Description: 
--
-- Dependencies:    none
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;


entity reg_PIO is
generic (width: integer :=15);
port (
    clk : in std_logic;
    we  : in std_logic;                                 --we=write enable(active high)
    D   : in std_logic_vector(width downto 0);      --data in
    Q   : out std_logic_vector(width downto 0);     --data out
    rst : in std_logic
);
end reg_PIO;

architecture registers of reg_PIO is 
begin

process (clk,rst)
begin
    if rst='1' then
        Q <= (others=>'0');
    elsif (rising_edge(clk) and we='1') then
        Q <= D;
    end if;
    
end process;
end registers;

