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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:41:41 02/25/2014 
-- Design Name: 
-- Module Name:    reg_PIO - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reg_PIO is
generic (width: integer :=15); --s tem bomo nastimal velikost s pomocjo generci mapa
port (
	clk:	in std_logic;
	we:	in std_logic;											--we=write enable(active high)
	D:		in std_logic_vector(width downto 0);		--data in
	Q:		out std_logic_vector(width downto 0);		--data out
	rst:	in std_logic
);
end reg_PIO;

architecture registers of reg_PIO is 
begin
process (clk,rst)
begin
	if rst='1' then
		Q<=(others=>'0');
	elsif (rising_edge(clk) and we='1') then
		Q <= D;
	end if;
	
end process;
end registers;

