----------------------------------------------------------------------------------
-- Company: IJS 
-- Engineer: Gasper Kojek
-- 
-- Create Date:    14:50:28 02/25/2014 
-- Last edit:      12:35    03/04/2014
-- Design Name:    BRAM block
-- Module Name:    reg_bram - bram 
-- Project Name: 
-- Target Devices:  Xilinx Virtex 5
-- Tool versions:   Xilinx ISE 14.7
-- Description: 
--
-- Dependencies:    none
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
--
-- Dual-Port RAM with Synchronous Read (Read Through)
--      16 x 64 bit
--
--
--
-- Read-First Mode
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

entity rams_11 is
   -- port definitions
   port( 
         clk        : in std_logic;
          
        --primary (PCIe)
        addr1       : in std_logic_vector (3 downto 0);
        out1A       : out std_logic_vector (63 downto 0);
        write_en1   : in std_logic;
        write_data1 : in std_logic_vector (63 downto 0);

        --dual (compressor core)
        addr2       : in std_logic_vector (3 downto 0);
        out2A       : out std_logic_vector (63 downto 0)
        );
end entity rams_11;
 
architecture syn of rams_11 is
    type   ram_type is array (15 downto 0) of std_logic_vector (63 downto 0);
    signal RAM    : ram_type;
    signal read_a : std_logic_vector(3 downto 0);
    signal read_b : std_logic_vector(3 downto 0);
begin

process (clk)
begin
    if (rising_edge(clk)) then
        if (write_en1 = '1') then
            RAM(conv_integer(addr1)) <= write_data1;
        end if;
        read_a <= addr1;
        read_b <= addr2;
    end if;
end process;

out1A <= RAM(conv_integer(read_a));
out2A <= RAM(conv_integer(read_b));


end syn;
