----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:15:27 03/05/2014 
-- Design Name: 
-- Module Name:    user_wrapper_for_pcie - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

entity user_wrapper_for_pcie is
port  (

	    --
    -- Common
    --

    trn_clk : in std_logic;
    trn_reset_n : in std_logic;
    trn_lnk_up_n : in std_logic;

    --
    -- Tx
    --

    trn_td : out std_logic_vector((64 - 1) downto 0);
    trn_trem_n : out std_logic_vector(7 downto 0);
    trn_tsof_n : out std_logic;
    trn_teof_n : out std_logic;
    trn_tsrc_rdy_n : out std_logic;
    trn_tdst_rdy_n : in std_logic;
    trn_tsrc_dsc_n : out std_logic;
    trn_terrfwd_n : out std_logic;
    trn_tdst_dsc_n : in std_logic;
    trn_tbuf_av : in std_logic_vector((4 - 1) downto 0);

    --
    -- Rx
    --

    trn_rd : in std_logic_vector((64 - 1) downto 0);
    trn_rrem_n: in std_logic_vector(7 downto 0);
    trn_rsof_n : in std_logic;
    trn_reof_n : in std_logic;
    trn_rsrc_rdy_n : in std_logic;
    trn_rsrc_dsc_n : in std_logic;
    trn_rdst_rdy_n : out std_logic;
    trn_rerrfwd_n : in std_logic;
    trn_rnp_ok_n : out std_logic;

    trn_rbar_hit_n : in std_logic_vector(6 downto 0);
    trn_rfc_nph_av : in std_logic_vector(7 downto 0);
    trn_rfc_npd_av : in std_logic_vector(11 downto 0);
    trn_rfc_ph_av : in std_logic_vector(7 downto 0)     ;
    trn_rfc_pd_av : in std_logic_vector(11 downto 0)    ;
    trn_rcpl_streaming_n      : out std_logic;

    ---------------------------------------------------------
    -- 3. Host (CFG) Interface
    ---------------------------------------------------------

    cfg_do : in std_logic_vector(31 downto 0);
    cfg_di : out std_logic_vector(31 downto 0);
    cfg_byte_en_n : out std_logic_vector(3 downto 0);
    cfg_dwaddr : out std_logic_vector(9 downto 0);
    cfg_rd_wr_done_n : in std_logic;
    cfg_wr_en_n : out std_logic;
    cfg_rd_en_n : out std_logic;
    cfg_err_cor_n : out std_logic;
    cfg_err_ur_n : out std_logic;
    cfg_err_cpl_rdy_n : in std_logic;
    cfg_err_ecrc_n : out std_logic;
    cfg_err_cpl_timeout_n : out std_logic;
    cfg_err_cpl_abort_n : out std_logic;
    cfg_err_cpl_unexpect_n : out std_logic;
    cfg_err_posted_n : out std_logic;
    cfg_interrupt_n : out std_logic;
    cfg_interrupt_rdy_n : in std_logic;

    cfg_interrupt_assert_n : out std_logic;
    cfg_interrupt_di : out std_logic_vector(7 downto 0);
    cfg_interrupt_do : in  std_logic_vector(7 downto 0);
    cfg_interrupt_mmenable : in  std_logic_vector(2 downto 0);
    cfg_interrupt_msienable: in  std_logic;

    cfg_turnoff_ok_n : out std_logic;
    cfg_to_turnoff_n : in std_logic;
    cfg_pm_wake_n : out std_logic;
    cfg_pcie_link_state_n : in std_logic_vector(2 downto 0);
    cfg_trn_pending_n : out std_logic;
    cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);

    cfg_bus_number : in std_logic_vector(7 downto 0);
    cfg_device_number : in std_logic_vector(4 downto 0);
    cfg_function_number : in std_logic_vector(2 downto 0);
    cfg_status : in std_logic_vector(15 downto 0);
    cfg_command : in std_logic_vector(15 downto 0);
    cfg_dstatus : in std_logic_vector(15 downto 0);
    cfg_dcommand : in std_logic_vector(15 downto 0);
    cfg_lstatus : in std_logic_vector(15 downto 0);
    cfg_lcommand : in std_logic_vector(15 downto 0)
 
);
end user_wrapper_for_pcie;

architecture Behavioral of user_wrapper_for_pcie is
-- --System
-- signal     sys_clk_c : std_logic;
-- signal     sys_reset_n_c : std_logic;

-- --TRN Common
-- signal     trn_clk_c : std_logic;
-- signal     trn_reset_n_c : std_logic;
-- signal     trn_lnk_up_n_c : std_logic;

-- --TX
-- signal     trn_tsof_n_c : std_logic;
-- signal     trn_teof_n_c : std_logic;
-- signal     trn_tsrc_rdy_n_c : std_logic;
-- signal     trn_tdst_rdy_n_c : std_logic;
-- signal     trn_tsrc_dsc_n_c : std_logic;
-- signal     trn_terrfwd_n_c : std_logic;
-- signal     trn_tdst_dsc_n_c : std_logic;
-- signal     trn_td_c : std_logic_vector((64 - 1) downto 0);
-- signal     trn_trem_n_c : std_logic_vector(7 downto 0);
-- signal     trn_tbuf_av_c : std_logic_vector(( 4 -1 )  downto 0);

-- --RX
-- signal     trn_rsof_n_c : std_logic;
-- signal     trn_reof_n_c : std_logic;
-- signal     trn_rsrc_rdy_n_c : std_logic;
-- signal     trn_rsrc_dsc_n_c : std_logic;
-- signal     trn_rdst_rdy_n_c : std_logic;
-- signal     trn_rerrfwd_n_c : std_logic;
-- signal     trn_rnp_ok_n_c : std_logic;
-- signal     trn_rd_c : std_logic_vector((64 - 1) downto 0);
-- signal     trn_rrem_n_c : std_logic_vector(7 downto 0);

-- signal     trn_rbar_hit_n_c : std_logic_vector(6 downto 0);
-- signal     trn_rfc_nph_av_c : std_logic_vector(7 downto 0);
-- signal     trn_rfc_npd_av_c : std_logic_vector(11 downto 0);
-- signal     trn_rfc_ph_av_c : std_logic_vector(7 downto 0);
-- signal     trn_rfc_pd_av_c : std_logic_vector(11 downto 0);
-- signal     trn_rcpl_streaming_n_c      : std_logic;

-- --CFG interface
-- signal     cfg_trn_pending_n_c : std_logic;
-- signal     cfg_do_c : std_logic_vector(31 downto 0);
-- signal     cfg_di_c : std_logic_vector(31 downto 0);
-- signal     cfg_dwaddr_c : std_logic_vector(9 downto 0) ;
-- signal     cfg_byte_en_n_c : std_logic_vector(3 downto 0);
-- signal     cfg_err_tlp_cpl_header_c : std_logic_vector(47 downto 0);
-- signal     cfg_wr_en_n_c : std_logic;
-- signal     cfg_rd_en_n_c : std_logic;
-- signal     cfg_rd_wr_done_n_c : std_logic;
-- signal     cfg_err_cor_n_c : std_logic;
-- signal     cfg_err_ur_n_c : std_logic;
-- signal     cfg_err_ecrc_n_c : std_logic;
-- signal     cfg_err_cpl_timeout_n_c : std_logic;
-- signal     cfg_err_cpl_abort_n_c : std_logic;
-- signal     cfg_err_cpl_unexpect_n_c : std_logic;
-- signal     cfg_err_posted_n_c : std_logic;

-- signal     cfg_err_cpl_rdy_n_c : std_logic;  
-- signal     cfg_interrupt_n_c : std_logic;
-- signal     cfg_interrupt_rdy_n_c : std_logic;

signal     cfg_interrupt_assert_n_c : std_logic;
signal     cfg_interrupt_di_c : std_logic_vector(7 downto 0);
signal     cfg_interrupt_do_c : std_logic_vector(7 downto 0);
signal     cfg_interrupt_mmenable_c : std_logic_vector(2 downto 0);
signal     cfg_interrupt_msienable_c: std_logic;

-- signal     cfg_turnoff_ok_n_c : std_logic;
-- signal     cfg_to_turnoff_n_c : std_logic;
-- signal     cfg_pm_wake_n_c : std_logic;
-- signal     cfg_pcie_link_state_n_c : std_logic_vector(2 downto 0);
-- signal     cfg_bus_number_c : std_logic_vector(7 downto 0);
-- signal     cfg_device_number_c : std_logic_vector(4 downto 0);
-- signal     cfg_function_number_c : std_logic_vector(2 downto 0);
-- signal     cfg_status_c : std_logic_vector(15 downto 0);
-- signal     cfg_command_c : std_logic_vector(15 downto 0);
-- signal     cfg_dstatus_c : std_logic_vector(15 downto 0);
-- signal     cfg_dcommand_c : std_logic_vector(15 downto 0);
-- signal     cfg_lstatus_c : std_logic_vector(15 downto 0);
-- signal     cfg_lcommand_c : std_logic_vector(15 downto 0);
signal      cfg_completer_id_c : std_logic_vector (15 downto 0);
signal      cfg_bus_mstr_enable_c : std_logic;
signal      cfg_ext_tag_en_c : std_logic;
signal      cfg_neg_max_lnk_width_c : std_logic_vector(5 downto 0);
signal      cfg_prg_max_payload_size_c : std_logic_vector(2 downto 0);
signal      cfg_max_rd_req_size_c : std_logic_vector(2 downto 0);
signal      cfg_rd_comp_bound_c : std_logic;

--RX/TX ENGINES communication - QUEUE
   --Inputs
   signal req_tc_rx : std_logic_vector(2 downto 0) := (others => '0');
   signal req_td_rx : std_logic := '0';
   signal req_ep_rx : std_logic := '0';
   signal req_attr_rx : std_logic_vector(1 downto 0) := (others => '0');
   signal req_len_rx : std_logic_vector(9 downto 0) := (others => '0');
   signal req_rid_rx : std_logic_vector(15 downto 0) := (others => '0');
   signal req_tag_rx : std_logic_vector(7 downto 0) := (others => '0');
   signal req_be_rx : std_logic_vector(7 downto 0) := (others => '0');
   signal req_addr_rx : std_logic_vector(12 downto 0) := (others => '0');
   signal req_compl_addr_err_rx : std_logic := '0';
   signal req_compl_with_data_rx : std_logic := '0';
   signal req_compl_rx : std_logic := '0';
   signal compl_done_tx : std_logic := '0';

 	--Outputs
   signal compl_done_rx : std_logic;
   signal req_tc_tx : std_logic_vector(2 downto 0);
   signal req_td_tx : std_logic;
   signal req_ep_tx : std_logic;
   signal req_attr_tx : std_logic_vector(1 downto 0);
   signal req_len_tx : std_logic_vector(9 downto 0);
   signal req_rid_tx : std_logic_vector(15 downto 0);
   signal req_tag_tx : std_logic_vector(7 downto 0);
   signal req_be_tx : std_logic_vector(7 downto 0);
   signal req_addr_tx : std_logic_vector(12 downto 0);
   signal req_compl_addr_err_tx : std_logic;
   signal req_compl_with_data_tx : std_logic;
   signal req_compl_tx : std_logic;
   
   
   signal trn_rdst_rdy_n_c1 : std_logic;
   signal trn_rdst_rdy_n_c2 : std_logic;

-- REG ACCESS
--Inputs
signal rst_c          : std_logic := '0';
signal data_w_c       : std_logic_vector(63 downto 0) := (others => '0');
signal addr_w_c       : std_logic_vector(4 downto 0) := (others => '0');
signal we_w_c         : std_logic := '0';
signal re_c           : std_logic := '0';
signal addr_r_c       : std_logic_vector(4 downto 0) := (others => '0');
signal addr_r_tx       : std_logic_vector(4 downto 0) := (others => '0');
signal addr_r_rx       : std_logic_vector(4 downto 0) := (others => '0');
signal bram_addr_r_c  : std_logic_vector(5 downto 0) := (others => '0');
signal bram_data_w_c  : std_logic_vector(15 downto 0) := (others => '0');
signal bram_addr_w_c  : std_logic_vector(5 downto 0) := (others => '0');
signal we_core_c      : std_logic := '0';
signal read_pck_len_c : std_logic_vector(9 downto 0) := (others => '0');
signal read_done_c    : std_logic := '0';
signal write_pck_len_c: std_logic_vector(9 downto 0) := (others => '0');
signal write_done_c   : std_logic := '0';
signal no_more_data_c : std_logic := '0';

--Outputs
signal addr_error_w_c : std_logic;
signal data_r_c       : std_logic_vector(63 downto 0);
signal data_r_valid_c : std_logic;
signal busy_tx_c      : std_logic;
signal addr_error_r_c : std_logic;
signal bram_data_r_c  : std_logic_vector(15 downto 0);
signal busy_r_c       : std_logic;
signal busy_w_c       : std_logic;
signal work_read_base_c   : std_logic_vector(63 downto 0);
signal work_read_count_c  : std_logic_vector(63 downto 0);
signal read_f_c       : std_logic;
signal work_write_base_c  : std_logic_vector(63 downto 0);
signal work_write_count_c : std_logic_vector(63 downto 0);
signal write_f_c      : std_logic;
signal freq_measure_c : std_logic;
signal adaptive_c     : std_logic;
signal int_no_data_c      : std_logic;
signal int_write_finished_c : std_logic;
signal int_read_finished_c     : std_logic;
signal addr_r_take_c        : std_logic;

component RX_ENGINE
port (
    -- Common
    trn_clk      : in std_logic;
    trn_reset_n  : in std_logic;
    trn_lnk_up_n : in std_logic;

    -- Rx
    trn_rd          : in std_logic_vector((64 - 1) downto 0); --receive daa
    trn_rrem_n      : in std_logic_vector(7 downto 0); --receive data remainder(if all 0 , data valid 63 downto 0, if 0x0F, data valid only on 63 downto 32)
    trn_rsof_n      : in std_logic; --receive start of frame
    trn_reof_n      : in std_logic; --receive end of frame
    trn_rsrc_rdy_n  : in std_logic; --active low-indicates pcie is presenting valid data
    trn_rsrc_dsc_n  : in std_logic; --not supported, tied high
    trn_rdst_rdy_n  : out std_logic; --active low-receive destination(user application) ready
    trn_rerrfwd_n   : in std_logic;  --active low-receive error forward-marks the packet in progress as poisoned
    trn_rnp_ok_n    : out std_logic; --receive non posted OK

    trn_rbar_hit_n  : in std_logic_vector(6 downto 0);  --active low-indicates BAR(s) targeted by current receive transaction
    trn_rfc_nph_av  : in std_logic_vector(7 downto 0);  --flow control
    trn_rfc_npd_av  : in std_logic_vector(11 downto 0); --flow control
    trn_rfc_ph_av   : in std_logic_vector(7 downto 0);  --flow control
    trn_rfc_pd_av   : in std_logic_vector(11 downto 0); --flow control
    trn_rcpl_streaming_n : out std_logic; --active low-receive completion streaming
    
    -- Register Access (write)
    data_w             : out std_logic_vector (63 downto 0);
    addr_w             : out std_logic_vector (4 downto 0);
    we_w               : out std_logic;
    addr_error_w       : in std_logic;
    busy_w             : in std_logic;
    -- Register Access (read)    
    data_r             : in std_logic_vector (63 downto 0);
    addr_r             : out std_logic_vector (4 downto 0);
    data_r_valid       : in std_logic;

    -- TX ENGINE communication
    req_compl_o             : out std_logic;
    req_compl_addr_err_o    : out std_logic; -- request completion with data: address error
    req_compl_with_data_o   : out std_logic; -- asserted indicates to generate a completion WITH data    
                                             -- otherwise a completion WITHOUT data will be generated
    compl_done_i            : in std_logic;  -- requested completion done
    
    -- from received TLP header:
    req_tc_o          : out std_logic_vector(2 downto 0);  -- Memory Read TC(traffic class field) 
    req_td_o          : out std_logic; -- Memory Read TD(TLP digest bit-ECRC)  - vedno 0?
    req_ep_o          : out std_logic; -- Memory Read EP(poisoned bit)         - not yet implemented
    req_attr_o        : out std_logic_vector(1 downto 0);  -- Memory Read Attribute
    req_len_o         : out std_logic_vector(9 downto 0);  -- Memory Read Length (1DW)
    req_rid_o         : out std_logic_vector(15 downto 0); -- Memory Read Requestor ID
    req_tag_o         : out std_logic_vector(7 downto 0);  -- Memory Read Tag
    req_be_o          : out std_logic_vector(7 downto 0);  -- Memory Read Byte Enables
    req_addr_o        : out std_logic_vector(12 downto 0)  -- Memory Read Address 
    );

end component;

component TX_ENGINE is
port (
    -- Common
    clk                      : in std_logic;
    rst_n                    : in std_logic;

    -- Tx
    trn_td                   : out std_logic_vector( 63 downto 0);
    trn_trem_n               : out std_logic_vector(7 downto 0);
    trn_tsof_n               : out std_logic;
    trn_teof_n               : out std_logic;
    trn_tsrc_rdy_n           : out std_logic;
    trn_tsrc_dsc_n           : out std_logic;
    trn_tdst_rdy_n           : in std_logic;
    trn_tdst_dsc_n           : in std_logic;

    -- RX ENGINE communication
    req_compl_i              : in std_logic;
    req_compl_addr_err_i     : in std_logic; -- requested completion with data: address error
    req_compl_with_data_i    : in std_logic;  -- asserted indicates to generate a completion WITH data
                                              -- otherwise a completion WITHOUT data will be generated
    compl_done_o             : out std_logic;

    -- from received TLP header:
    req_tc_i                 : in std_logic_vector(2 downto 0);
    req_td_i                 : in std_logic;
    req_ep_i                 : in std_logic;
    req_attr_i               : in std_logic_vector(1 downto 0);
    req_len_i                : in std_logic_vector(9 downto 0);
    req_rid_i                : in std_logic_vector(15 downto 0);
    req_tag_i                : in std_logic_vector(7 downto 0);
    req_be_i                 : in std_logic_vector(7 downto 0);
    req_addr_i               : in std_logic_vector(12 downto 0);
    
    -- Settings
    completer_id_i           : in std_logic_vector(15 downto 0);
    cfg_bus_mstr_enable_i    : in std_logic;

    -- Register Access
    data_r                   : in  std_logic_vector (63 downto 0);
    addr_r                   : out std_logic_vector (4 downto 0);
    busy_tx                  : in  std_logic;
    addr_error_r             : in  std_logic;
    re                       : out std_logic;
    addr_r_take_o            : out std_logic

);
end component;

component RX_TX_QUEUE is
port (
    clk                     : in std_logic;
    rst                     : in std_logic;

    -- from received TLP header - RX SIDE connections:
    req_tc_rx               : in std_logic_vector(2 downto 0);  -- Memory Read TC(traffic class field)
    req_td_rx               : in std_logic;                     -- Memory Read TD(TLP digest bit-ECRC)
    req_ep_rx               : in std_logic;                     -- Memory Read EP(poisoned bit)
    req_attr_rx             : in std_logic_vector(1 downto 0);  -- Memory Read Attribute
    req_len_rx              : in std_logic_vector(9 downto 0);  -- Memory Read Length (1DW)
    req_rid_rx              : in std_logic_vector(15 downto 0); -- Memory Read Requestor ID
    req_tag_rx              : in std_logic_vector(7 downto 0);  -- Memory Read Tag
    req_be_rx               : in std_logic_vector(7 downto 0);  -- Memory Read Byte Enables
    req_addr_rx             : in std_logic_vector(12 downto 0); -- Memory Read Address 
    req_compl_addr_err_rx   : in std_logic; -- requested completion with data: address error
    req_compl_with_data_rx  : in std_logic;  -- asserted indicates to generate a completion WITH data
                                              -- otherwise a completion WITHOUT data will be generated
    req_compl_rx            : in std_logic;                                                
    compl_done_rx           : out std_logic;
    rx_queue_full_n           : out std_logic;
    
    
    --  from DMA engine:
    
    --to TX:
    req_tc_tx               : out std_logic_vector(2 downto 0);  -- Memory Read TC(traffic class field)
    req_td_tx               : out std_logic;                     -- Memory Read TD(TLP digest bit-ECRC)
    req_ep_tx               : out std_logic;                     -- Memory Read EP(poisoned bit)
    req_attr_tx             : out std_logic_vector(1 downto 0);  -- Memory Read Attribute
    req_len_tx              : out std_logic_vector(9 downto 0);  -- Memory Read Length (1DW)
    req_rid_tx              : out std_logic_vector(15 downto 0); -- Memory Read Requestor ID
    req_tag_tx              : out std_logic_vector(7 downto 0);  -- Memory Read Tag
    req_be_tx               : out std_logic_vector(7 downto 0);  -- Memory Read Byte Enables
    req_addr_tx             : out std_logic_vector(12 downto 0); -- Memory Read Address 
    req_compl_addr_err_tx   : out std_logic;  -- requested completion with data: address error
    req_compl_with_data_tx  : out std_logic;  -- asserted indicates to generate a completion WITH data
                                              -- otherwise a completion WITHOUT data will be generated
    req_compl_tx            : out std_logic;    
    compl_done_tx           : in std_logic   

);
end component;

COMPONENT reg_access is
     generic( REG_WIDTH:integer:=64 );
port (
        clk                : in std_logic;
        rst                : in std_logic; --active high
        
    --For RX ENGINE
        data_w             : in std_logic_vector (63 downto 0);
        addr_w             : in std_logic_vector (4 downto 0);
        we_w               : in std_logic;
        addr_error_w       : out std_logic;
        busy_w             : out std_logic;
        
        
    --For TX ENGINE
        data_r             : out std_logic_vector (63 downto 0);
        addr_r             : in  std_logic_vector (4 downto 0);
        busy_tx            : out std_logic;
        addr_error_r       : out std_logic;
        re                 : in  std_logic; --read enable - is high when pcie reads data from registers
        
    --BRAM - Comp Core side
        bram_data_r        : out std_logic_vector (15 downto 0);
        bram_addr_r        : in  std_logic_vector (5 downto 0);
        bram_data_w        : in  std_logic_vector (15 downto 0);
        bram_addr_w        : in  std_logic_vector (5 downto 0);
        we_core            : in  std_logic;
        busy_r             : out std_logic;

        
    --registri
        --read
        work_read_base     : out std_logic_vector (REG_WIDTH-1 downto 0);
        work_read_count    : out std_logic_vector (REG_WIDTH-1 downto 0);
        read_pck_len       : in  std_logic_vector (9 downto 0);
        read_f             : out std_logic; --is high while read is not finished(read count is not zero)
        read_done          : in  std_logic; --is high for 1 clock when a packet is read
        
        --write
        work_write_base    : out std_logic_vector (REG_WIDTH-1 downto 0);
        work_write_count   : out std_logic_vector (REG_WIDTH-1 downto 0);
        write_pck_len      : in  std_logic_vector (9 downto 0);
        write_f            : out std_logic;
        write_done         : in  std_logic;
        no_more_data       : in  std_logic;
        
        --settings
        freq_measure       : out std_logic;
        adaptive           : out std_logic;
            --interrupt masks
        int_no_data        : out std_logic;
        int_write_finished : out std_logic;
        int_read_finished  : out std_logic
        
        
);
END COMPONENT;

component PIO_TO_CTRL
port (

  clk : in std_logic;
  rst_n : in std_logic;

  req_compl_i : in std_logic;
  compl_done_i : in std_logic;

  cfg_to_turnoff_n : in std_logic;
  cfg_turnoff_ok_n : out std_logic
);
end component;

begin

  -- Core input tie-offs


  trn_terrfwd_n             <= '1';

  cfg_err_cor_n             <= '1';
  cfg_err_ur_n              <= '1';
  cfg_err_ecrc_n            <= '1';
  cfg_err_cpl_timeout_n     <= '1';
  cfg_err_cpl_abort_n       <= '1';
  cfg_err_cpl_unexpect_n    <= '1';
  cfg_err_posted_n          <= '0';
  cfg_interrupt_n           <= '1'; --FIXME for bmd

  cfg_interrupt_assert_n <= '0'; --FIXME for bmd
  cfg_interrupt_di <= X"00";

  cfg_pm_wake_n             <= '1';
  cfg_trn_pending_n         <= '1';
  cfg_dwaddr                <= (others => '0'); --FIXME for bmd
  cfg_err_tlp_cpl_header    <= (others => '0');
  cfg_di                    <= (others => '0');
  cfg_byte_en_n             <= X"F"; -- 4-bit bus
  cfg_wr_en_n               <= '1';
  cfg_rd_en_n               <= '1'; --FIXME for bmd
  cfg_completer_id_c        <= (cfg_bus_number &
                                cfg_device_number &
                                cfg_function_number);
  cfg_bus_mstr_enable_c     <= cfg_command(2);
  cfg_ext_tag_en_c          <= cfg_dcommand(8);
  cfg_neg_max_lnk_width_c   <= cfg_lstatus(9 downto 4);
  cfg_prg_max_payload_size_c<= cfg_dcommand(7 downto 5);
  cfg_max_rd_req_size_c     <= cfg_dcommand(14 downto 12);
  cfg_rd_comp_bound_c       <= cfg_lcommand(3);
  
  
rst_c<=not trn_reset_n;
addr_r_c <= addr_r_tx when addr_r_take_c='1' else addr_r_rx;
data_r_valid_c <= not addr_r_take_c;
trn_rdst_rdy_n <= trn_rdst_rdy_n_c1 and trn_rdst_rdy_n_c2;

RX: RX_ENGINE port map (
--
-- Transaction ( TRN ) Interface
--
    trn_clk => trn_clk,                   -- I
    trn_reset_n => trn_reset_n,           -- I
    trn_lnk_up_n => trn_lnk_up_n,         -- I
  
  -- Rx Local-Link
    trn_rd => trn_rd,                     -- I (63/31:0)
    trn_rrem_n => trn_rrem_n,             -- I
    trn_rsof_n => trn_rsof_n,             -- I
    trn_reof_n => trn_reof_n,             -- I
    trn_rsrc_rdy_n => trn_rsrc_rdy_n,     -- I
    trn_rsrc_dsc_n => trn_rsrc_dsc_n,     -- I
    trn_rdst_rdy_n => trn_rdst_rdy_n_c1,     -- O
    trn_rerrfwd_n => trn_rerrfwd_n,       -- I
    trn_rnp_ok_n => trn_rnp_ok_n,         -- O

    trn_rbar_hit_n => trn_rbar_hit_n,     -- I (6:0)
    trn_rfc_nph_av => trn_rfc_nph_av,     -- I (7:0)
    trn_rfc_npd_av => trn_rfc_npd_av,     -- I (11:0)
    trn_rfc_ph_av => trn_rfc_ph_av,       -- I (7:0)
    trn_rfc_pd_av => trn_rfc_pd_av,       -- I (11:0)
    trn_rcpl_streaming_n => trn_rcpl_streaming_n, --O
  
  --registers
    data_w => data_w_c,                   --O
    addr_w => addr_w_c,                   --O
    we_w => we_w_c,                       --O
    addr_error_w => addr_error_w_c,       --I
    busy_w => busy_w_c,                   --I
    
    data_r => data_r_c,                  --I(63:0)
    addr_r => addr_r_rx,                  --O
    data_r_valid => data_r_valid_c,
    
  --TX ENGINE communication
    req_compl_o => req_compl_rx,           --O
    req_compl_addr_err_o => req_compl_addr_err_rx,   --O
    req_compl_with_data_o => req_compl_with_data_rx, --O
    compl_done_i => compl_done_rx,         --I
    req_tc_o => req_tc_rx,                 --O(2:0)
    req_td_o => req_td_rx,                 --O
    req_ep_o => req_ep_rx,                 --O
    req_attr_o => req_attr_rx,             --O(1:0)
    req_len_o => req_len_rx,               --O(9:0)
    req_rid_o => req_rid_rx,               --O(15:0)
    req_tag_o => req_tag_rx,               --O(7:0)
    req_be_o => req_be_rx,                 --O(7:0)
    req_addr_o => req_addr_rx              --O(12:0)
);

-- cfg_completer_id_c<=cfg_bus_number & cfg_device_number & cfg_function_number;
TX: TX_ENGINE port map (
    clk => trn_clk,                     -- I
    rst_n => trn_reset_n,               -- I

    -- LocalLink Tx
    trn_td => trn_td,               -- O [63:0]
    trn_trem_n => trn_trem_n,       -- O [7:0]
    trn_tsof_n => trn_tsof_n,           -- O
    trn_teof_n => trn_teof_n,           -- O
    trn_tsrc_dsc_n => trn_tsrc_dsc_n,   -- O
    trn_tsrc_rdy_n => trn_tsrc_rdy_n,   -- O
    trn_tdst_dsc_n => trn_tdst_dsc_n,   -- I
    trn_tdst_rdy_n => trn_tdst_rdy_n,   -- I

  --RX ENGINE communication
    req_compl_i => req_compl_tx,           -- I
    req_compl_addr_err_i => req_compl_addr_err_tx,
    req_compl_with_data_i => req_compl_with_data_tx, -- I
    compl_done_o => compl_done_tx,         -- 0
    req_tc_i => req_tc_tx,                 -- I [2:0]
    req_td_i => req_td_tx,                 -- I
    req_ep_i => req_ep_tx,                 -- I
    req_attr_i => req_attr_tx,             -- I [1:0]
    req_len_i => req_len_tx,               -- I [9:0]
    req_rid_i => req_rid_tx,               -- I [15:0]
    req_tag_i => req_tag_tx,               -- I [7:0]
    req_be_i => req_be_tx,                 -- I [7:0]
    req_addr_i => req_addr_tx,             -- I [12:0]
    
  -- Settings
    completer_id_i => cfg_completer_id_c,          -- I [15:0]
    cfg_bus_mstr_enable_i => cfg_bus_mstr_enable_c,-- I
                    
  -- registers
    data_r => data_r_c,                 -- I [63:0]
    addr_r => addr_r_tx,                 -- O [5:0]
    busy_tx => busy_tx_c,               -- I
    addr_error_r => addr_error_r_c,     -- I
    re => re_c,                         -- O  
    addr_r_take_o=>addr_r_take_c        --O
 );
 
Queue: RX_TX_QUEUE port map (
    clk=>trn_clk,
    rst=>rst_c,
    req_tc_rx => req_tc_rx,
    req_td_rx => req_td_rx,
    req_ep_rx => req_ep_rx,
    req_attr_rx => req_attr_rx,
    req_len_rx => req_len_rx,
    req_rid_rx => req_rid_rx,
    req_tag_rx => req_tag_rx,
    req_be_rx => req_be_rx,
    req_addr_rx => req_addr_rx,
    req_compl_addr_err_rx => req_compl_addr_err_rx,
    req_compl_with_data_rx => req_compl_with_data_rx,
    req_compl_rx => req_compl_rx,
    compl_done_rx => compl_done_rx,
    rx_queue_full_n => trn_rdst_rdy_n_c2,
    req_tc_tx => req_tc_tx,
    req_td_tx => req_td_tx,
    req_ep_tx => req_ep_tx,
    req_attr_tx => req_attr_tx,
    req_len_tx => req_len_tx,
    req_rid_tx => req_rid_tx,
    req_tag_tx => req_tag_tx,
    req_be_tx => req_be_tx,
    req_addr_tx => req_addr_tx,
    req_compl_addr_err_tx => req_compl_addr_err_tx,
    req_compl_with_data_tx => req_compl_with_data_tx,
    req_compl_tx => req_compl_tx,
    compl_done_tx => compl_done_tx
);

Registers: reg_access PORT MAP (
      clk => trn_clk,
      rst => rst_c,
      data_w => data_w_c,
      addr_w => addr_w_c,
      we_w => we_w_c,
      addr_error_w => addr_error_w_c,
      busy_w => busy_w_c,
      re => re_c,
      data_r => data_r_c,
      addr_r => addr_r_c,
      busy_tx => busy_tx_c,
      addr_error_r => addr_error_r_c,
      bram_data_r => bram_data_r_c,
      bram_addr_r => bram_addr_r_c,
      bram_data_w => bram_data_w_c,
      bram_addr_w => bram_addr_w_c,
      we_core => we_core_c,
      busy_r => busy_r_c,
      work_read_base => work_read_base_c,
      work_read_count => work_read_count_c,
      read_pck_len => read_pck_len_c,
      read_f => read_f_c,
      read_done => read_done_c,
      work_write_base => work_write_base_c,
      work_write_count => work_write_count_c,
      write_pck_len => write_pck_len_c,
      write_f => write_f_c,
      write_done => write_done_c,
      no_more_data => no_more_data_c,
      freq_measure => freq_measure_c,
      adaptive => adaptive_c,
      int_no_data => int_no_data_c,
      int_write_finished => int_write_finished_c,
      int_read_finished => int_read_finished_c
);
    
PIO_2_CTRL : PIO_TO_CTRL port map   (

   clk => trn_clk,                             -- I
   rst_n => trn_reset_n,                       -- I

   req_compl_i => req_compl_tx,                   -- I
   compl_done_i => compl_done_tx,                 -- I

   cfg_to_turnoff_n => cfg_to_turnoff_n,       -- I
   cfg_turnoff_ok_n => cfg_turnoff_ok_n        -- O

);



end Behavioral;

