Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'user_wrapper_for_pcie'

Design Information
------------------
Command Line   : map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol
high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr
off -lc off -power off -o user_wrapper_for_pcie_map.ncd
user_wrapper_for_pcie.ngd user_wrapper_for_pcie.pcf 
Target Device  : xc5vlx110t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.55 $
Mapped Date    : Fri Mar 07 15:27:03 2014

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 15 secs 
Total CPU  time at the beginning of Placer: 14 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:908885) REAL time: 17 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:908885) REAL time: 17 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:908885) REAL time: 17 secs 

Phase 4.37  Local Placement Optimization
Phase 4.37  Local Placement Optimization (Checksum:908885) REAL time: 17 secs 

Phase 5.33  Local Placement Optimization
Phase 5.33  Local Placement Optimization (Checksum:908885) REAL time: 17 secs 

Phase 6.32  Local Placement Optimization
Phase 6.32  Local Placement Optimization (Checksum:908885) REAL time: 18 secs 

Phase 7.2  Initial Clock and IO Placement
...
...
Phase 7.2  Initial Clock and IO Placement (Checksum:b385f66f) REAL time: 20 secs 

Phase 8.36  Local Placement Optimization
Phase 8.36  Local Placement Optimization (Checksum:b385f66f) REAL time: 20 secs 

Phase 9.30  Global Clock Region Assignment
Phase 9.30  Global Clock Region Assignment (Checksum:b385f66f) REAL time: 20 secs 

Phase 10.3  Local Placement Optimization
....
Phase 10.3  Local Placement Optimization (Checksum:135ef687) REAL time: 21 secs 

Phase 11.5  Local Placement Optimization
Phase 11.5  Local Placement Optimization (Checksum:135ef687) REAL time: 21 secs 

Phase 12.8  Global Placement
...............................
.......
Phase 12.8  Global Placement (Checksum:ff401891) REAL time: 23 secs 

Phase 13.29  Local Placement Optimization
Phase 13.29  Local Placement Optimization (Checksum:ff401891) REAL time: 23 secs 

Phase 14.5  Local Placement Optimization
Phase 14.5  Local Placement Optimization (Checksum:ff401891) REAL time: 23 secs 

Phase 15.18  Placement Optimization
Phase 15.18  Placement Optimization (Checksum:34220caf) REAL time: 48 secs 

Phase 16.5  Local Placement Optimization
Phase 16.5  Local Placement Optimization (Checksum:34220caf) REAL time: 48 secs 

Phase 17.34  Placement Validation
Phase 17.34  Placement Validation (Checksum:34220caf) REAL time: 48 secs 

Total REAL time to Placer completion: 48 secs 
Total CPU  time to Placer completion: 47 secs 
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net TX/byte_count_cmp_eq0000 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    1
Slice Logic Utilization:
  Number of Slice Registers:                   885 out of  69,120    1%
    Number used as Flip Flops:                 875
    Number used as Latches:                     10
  Number of Slice LUTs:                      1,626 out of  69,120    2%
    Number used as logic:                    1,625 out of  69,120    2%
      Number using O6 output only:           1,351
      Number using O5 output only:               4
      Number using O5 and O6:                  270
    Number used as exclusive route-thru:         1
  Number of route-thrus:                         5
    Number using O6 output only:                 5

Slice Logic Distribution:
  Number of occupied Slices:                   543 out of  17,280    3%
  Number of LUT Flip Flop pairs used:        1,639
    Number with an unused Flip Flop:           754 out of   1,639   46%
    Number with an unused LUT:                  13 out of   1,639    1%
    Number of fully used LUT-FF pairs:         872 out of   1,639   53%
    Number of unique control sets:              23
    Number of slice register sites lost
      to control set restrictions:              35 out of  69,120    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                       172 out of     640   26%

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                       2 out of     148    1%
    Number using BlockRAM only:                  2
    Total primitives used:
      Number of 36k BlockRAM used:               2
    Total Memory used (KB):                     72 out of   5,328    1%
  Number of BUFG/BUFGCTRLs:                      1 out of      32    3%
    Number used as BUFGs:                        1

Average Fanout of Non-Clock Nets:                5.45

Peak Memory Usage:  668 MB
Total REAL time to MAP completion:  50 secs 
Total CPU time to MAP completion:   49 secs 

Mapping completed.
See MAP report file "user_wrapper_for_pcie_map.mrp" for details.
