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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:02:12 02/25/2014 
-- Design Name: 
-- Module Name:    ram_wrap - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ram_wrap is
	port (
			clk : in std_logic;
			
			--Primary port :  (iz kompresor core)			
			addr_wr1 		: in std_logic_vector(5 downto 0);				--6 bitni addres iz kompresorja (5 downto 2)-tapravi address za v ram;(1 downto 0) dejansko kater blok 16 bitov rabimo
			write_en1 		: in std_logic;										--write enable (primary) - kompresor core
			write_data1 	: in unsigned(15 downto 0);				--16 data input iz kompresor core-a
			addr_rd1 		: in std_logic_vector(5 downto 0);
			out1 				: out unsigned(15 downto 0);			--16 bitni out do kompresor core-a	
			busy1				: out std_logic;
			
			--Dual port :   (pcie)
			addr_wr2 		: in std_logic_vector(3 downto 0);				--4 bitni addres iz pcie 
			write_en2		: in std_logic;										--write enable (dual) - pcie
			write_data2 	: in unsigned(63 downto 0);				--64 data input iz pcie
			addr_rd2 		: in std_logic_vector(3 downto 0);	
			out2 				: out unsigned(63 downto 0); 			--64 bitni out do pcie
			busy2				: out std_logic
);
end ram_wrap;

-- BRAM, 16 x 64 bitov
architecture Behavioral of ram_wrap is
component rams_11 
   port( 
	     clk         : in std_logic;
		  
		  --primary (kompresor core)
        addr1       : in std_logic_vector(3 downto 0);
        out1A       : out unsigned(63 downto 0);
		  write_en1   : in std_logic;
        write_data1 : in unsigned(63 downto 0);

		  --dual (pcie)
		  addr2       : in std_logic_vector(3 downto 0);
        out2A       : out unsigned(63 downto 0);
        write_en2   : in std_logic;
        write_data2 : in unsigned(63 downto 0)
        );
end component;

signal dout1 : unsigned (63 downto 0);	--prebrano iz rama(za kompresor), 
signal din1  : unsigned (63 downto 0); 	--v ta signal zlepimo za zapis iz kompresorja
signal addr1 : std_logic_vector(5 downto 0);
signal addr2 : std_logic_vector(3 downto 0);
signal dout1_std : std_logic_vector (63 downto 0);	--prebrano iz rama(za kompresor), 
signal out2_std  : std_logic_vector (63 downto 0); 	--v ta signal zlepimo za zapis iz kompresorja

begin
dout1<=unsigned(dout1_std);
din1<=unsigned(out2_std);
ram: rams_11 port map (
	clk=>clk,
	
	addr1=>addr1(5 downto 2),
	out1A=>dout1,
	write_en1=>write_en1,
	write_data1=>din1,
	
	addr2=>addr2,
	out2A=>out2,
	write_en2=>write_en2,
	write_data2=>write_data2

);

busy1<=write_en1;
busy2<=write_en2;
addr1<=addr_wr1 when write_en1='1' else addr_rd1;
addr2<=addr_wr2 when write_en2='1' else addr_rd2;

process (clk)
begin
if (rising_edge(clk)) then
	case ( addr1(1 downto 0) ) is
		when "00" =>
			out1<=dout1(15 downto 0);
			din1<=dout1(63 downto 16) & write_data1;
		when "01" =>
			out1<=dout1(31 downto 16);
			din1<=dout1(63 downto 32) & write_data1 & dout1(15 downto 0);
		when "10" =>
			out1<=dout1(47 downto 32);
			din1<=dout1(63 downto 48) & write_data1 & dout1(31 downto 0);
		when others =>
			out1<=dout1(63 downto 48);
			din1<=write_data1 & dout1(47 downto 0);
	end case;
--	if write_en1='1' then
--		addr1<=addr_wr1;
--	else addr1<=addr_rd1;
--	end if;
--	if write_en2='1' then
--		addr2<=addr_wr2;
--	else addr2<= addr_rd2;
--	end if;
	
end if;
end process;


end Behavioral;

