XILINX_PCI_EXP_EP Project Status (06/01/2014 - 01:00:03)
Project File: | PCIe_Bus_master_xil_vhdl.xise | Parser Errors: | No Errors
Module Name: | reg_access | Implementation State: | Synthesized
Target Device: | xc5vlx110t-1ff1136 |

- Errors:

No Errors
Product Version: | ISE 14.7 |

- Warnings:

13 Warnings (13 new)
Design Goal: | Balanced |

- Routing Results:

Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

Environment: | System Settings |

- Final Timing Score:

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice Registers | 591 | 69120 | 0%
Number of Slice LUTs | 1368 | 69120 | 1%
Number of fully used LUT-FF pairs | 586 | 1373 | 42%
Number of bonded IOBs | 478 | 640 | 74%
Number of Block RAM/FIFO | 2 | 148 | 1%
Number of BUFG/BUFGCTRLs | 1 | 32 | 3%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | ned 1. jun 01:00:02 2014 | 0 | 13 Warnings (13 new) | 1 Info (1 new)
Translation Report | Out of Date | tor 4. mar 12:07:06 2014 |  |  |
Map Report | Out of Date | tor 4. mar 12:08:19 2014 |  |  |
Place and Route Report | Out of Date | tor 4. mar 12:09:13 2014 |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Out of Date | tor 4. mar 12:09:32 2014 |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | čet 13. mar 15:28:16 2014
WebTalk Report | Out of Date | sre 12. mar 15:14:13 2014
WebTalk Log File | Out of Date | sre 12. mar 15:14:20 2014

Date Generated: 06/01/2014 - 01:00:04